During manufacturing of integrated circuits, various testing steps are wellknown for ensuring that the finished product will perform reliably and comply with applicable specifications. One set of tests are carried out at the "wafer sort" stage of a manufacturing process. Because silicon wafers are much larger than the individual integrated circuits formed on them, many such circuits are formed on a given wafer. The individual circuits are all formed at the same time as the photolithographic masks used in the manufacturing process contain many iterations of the individual circuit design, created by a step and repeat process.
After the various processing steps have been completed so as to form these multiple integrated circuits on a single wafer, the individual circuits are tested by connecting the lead bonding pads to suitable test equipment using fine wires or probes. When the test equipment detects a bad circuit, that individual die is marked, typically with red ink, to identify this fact. Subsequently, after the wafer is cut apart into individual die, those die that have red marks are discarded. This wafer sorting saves the substantial cost of packaging, further handling and final test of circuits already known to be defective. Die marking with ink is not especially convenient or efficient, however, and the industry trend is moving toward an inkless sort--where automated test and handling equipment simply places bad chips in a corresponding bin without physically marking them. Inkless sort procedures have the disadvantage that it is impossible to distinguish good chips from bad by visual inspection. Consequently, if a bad die is accidentally mixed in with good die, it will proceed to subsequent processing and packaging steps.
After integrated circuit devices have been packaged, they undergo final testing. Some portion of the circuits that passed the wafer sort inspection will nonetheless fail at final test because they may have been damaged in handling or in the packaging process itself, or the packaging and bonding may be defective. In some cases, final testing may simply be more comprehensive than wafer sort. Although one could mark an integrated circuit on the exterior of the package to identify a defective device at final test, this is not commonly done. Rather, the devices that fail at final test are simply collected in the reject bin or pile. Those devices are discarded or recycled.
One problem with this well-known technology, however, is that "bad" ICs, i.e., those that failed final test, sometimes "escape" from the manufacturer and are shipped to customers. On the other hand, some devices that passed final test nonetheless fail in the field. When failed devices are returned to the manufacturer, it attempts the determine what caused the failure, so that it can continually improve upon and refine its circuit designs, manufacturing processes and quality assurance program. Failure analysis is often difficult and time consuming, and therefore expensive. When the failure mode cannot be determined through electrical testing at the device pins, it becomes necessary to break open the IC package to conduct a more detailed examination. In those cases where the device was bad to begin with, i.e, it had actually failed final testing but escaped to the customer, much time is wasted in failure analysis. That effort and expense could be avoided if the manufacturer could readily identify those integrated circuits that had failed final test but nonetheless were shipped inadvertently.
Moreover, the return of devices which were known to be bad before they were shipped corrupts statistical data with respect to reliability of the devices in question. The need remains, therefore, for ways to mark integrated circuits so as to form a permanent record of manufacturing test results. Moreover, if that record of test results can be accessed or read electrically, the identification of such devices could be accomplished quickly and automatically so that time is not wasted in failure analysis of those devices.
A related problem occurs in the context of sorting or selecting devices based on their operating speed. Many semiconductor integrated circuits are commercially available in more than one grade or speed specification. In some cases, the circuit design for the various grades are the same. The finished parts are simply tested and sorted according to operating speed, as faster devices are necessary or desirable in some applications, and generally command a premium price. As in other types of final testing, devices that have been tested and sorted according to speed are sometimes mishandled, and may be packaged or marked with a speed designation that is incorrect. Devices that are basically functional but fail to meet speed specifications are sometimes returned to the factory.
When devices are returned to the manufacturer because they fail to meet speed specifications, the failure analysis department again faces the challenging task of determining the cause of that failure. In some cases, as noted, there may have been no failure at all. Rather, the device was simply mismarked or misdirected at final test. It would be beneficial, therefore, if the manufacturer could readily and accurately determine what speed tests a returned device actually passed before it was shipped. For example, if a device was sold as being operational up to 100 megahertz ("MHz"), and then returned to the manufacturer because the customer found it operated only up to 85 MHz, the manufacturer certainly would want to determine the cause of the problem. If the failure analysis people could readily determine that the particular device only passed final testing at 60 MHz, there would be no need to investigate further. There actually was no failure.
Another test that is often applied to semiconductor integrated circuits is a quiescent current test. Excessive quiescent current is generally an indicator of a defect in a semiconductor device. Accordingly, a maximum quiescent current value typically is selected by the manufacturer for testing purposes, and devices that draw quiescent current greater than that specification are rejected. However, statistical data indicate that there is a marginal range of quiescent current, although below the maximum permissible value, in which failure is more likely. It would assist in failure analysis for the manufacturer to be able to ascertain what the quiescent current value of a failed device was at the time of final test when the device was functioning properly.